1. Field of the Invention
The present invention relates in general to the manufacture of semiconductor integrated circuits. More particularly, it relates to a novel damascene interconnect process to avoid junction leakage.
2. Description of the Related Arts
Damascene is an interconnect fabrication process in which trenches for metal lines are etched in an interlevel dielectric (ILD) layer and filed with metal. The excess metal on the surface is removed and a planar structure with metal inlays in the dielectric layer is achieved. This process has several advantages over the traditional metal/ILD/planarization approach: (1) the surface at any time is totally flat; (2) the process eliminates the difficulty in filling small gaps between metal wires; and (3) it eliminates the difficulty in metal etching.
Damascene has been demonstrated in a number of applications. The most commonly applied process is the local interconnect. However, as shown in FIG. 1, once the process is applied in local interconnect 100 between different active areas, the edges 201 of isolation regions 200 result in large junction leakage. In semiconductor memory devices, the interconnect junction leakage become a critical issue for data storage. Thus, the aim of the present invention is to eliminate the disadvantages of the conventional approach while keeping the benefits of the damascene local interconnect.